| | | | PCI Express is a next generation PCI enhancement, and is here to stay. Express is now a serial bus inter-connect I/O technology, along with associated speed, protocol, and capabilities enhancements well beyond PCI and PCI-X. Express is an extension of the PCI Base Specification and maintains binary backwards compatibility with previous versions of the PCI and PCI-X Specification. Dashcourses four-day PCI Express course will cover the PCI-SIG‘s PCI Express Base Specification, including version 2.0 changes/enhancements. Emphasized material will include the details of the new PCI Express protocol stack for Express devices, including, protocol layer functions and formats, transaction details, and configuration requirements. Also presented are the 2.0 changes including Trusted Configuration Environment, Trusted Configuration Access Method, Trusted Computing Group, and Trusted Platform Module or TCE, TCAM, TCG and TPM. Legacy and native PCI Express devices and power management, fabric topology, switching and the use of virtual channels, which provide the ability to allocate bandwidth and support isochronous applications, will be discussed. | | | | | | Course Objectives In this course you will: - Learn about PCI Express fabric topology, the terms and definitions
- Understand the PCI Express protocol including layer definitions and layer relationships
- Traffic types defined by PCI Express and the meaning and usage of isochronous traffic
- The PCI Express definition of ‘virtual channels’ and PCI Express configuration
- Compatibility requirements with PCI and PCI-X, and PCI Express new enhanced features
- Understand the parallel/serial paradigm shift and PCI Express capabilities relative to other serial hardware/software architects
- Learn the Virtual Channel register set and how to program this register set to differentiate services (category of service/quality of service system capabilities)
- Serial protocol analyzer usage in design and debug, validation, and testing
| | | | | | Workshops/Demos Please contact us for information on workshops and demos included in this class. | | | | | | Who Should Attend? This 4-day PCI Express course is designed to provide a detailed understanding of the PCI Express technology as it relates to board, platform, and system design issues as well as to BIOS, device driver and application programmers, and test and de-bug issues. It is appropriate for design, debug, validation, and field engineers, and managers wanting a good understanding of the hardware/software capabilities and the disciplines required for successful introduction and support of PCI Express devices or systems. | | | | | | Course Prerequisites Participants should have attended the Dashcourses three-day PCI/PCI-X course or have a good working understanding of PCI 2.2 or later. Knowledge of the related PCI supporting specifications as defined by the PCI Special Interest Group (PCI SIG) is helpful but not required. |
Course Outline PCI Express Architectural Overview | | This chapter will provide the only review of PCI/PCI-X; only the essential concepts relative to PCI Express will be presented. Performance enhancements (real and hyped) will be discussed and explained. All the PCI Express architectural components will be defined. The chapter will serve as an overview of the rest of the class with specific details explained in related chapters. | | - Next Generation PCI
- Compatibility with Existing PCI Specification
- PCI
- PCI-X
- PCI Compatibility Software
- Ability to enumerate and configure PCI Express hardware using PCI system configuration software with no modifications
- Performance Enhancements
- Low-overhead, low-latency point-to-point communications
- Support for different traffic types I
- sochronous traffic support
- Support for differentiated serviced
- Hot Plug and Hot Swap Support
- Multi-hierarchy topology Support
- PCI Express System Architecture
- High speed serial interconnect
- PCI Express Protocol Stack
- Device types
- Legacy and native Power Management Support
- INTx Emulation and MSI Support
- Error Signaling and Logging
- Virtual Channel Support
| | | Serial/Parallel Paradigm | | | This chapter is not part of the specification, but an explanation of major differences between parallel and high speed serial interconnects. Clocking and signal differences, and diagnostic tools are emphasized. A comparison between different serial protocols presented. | | - Serial vs. Parallel Communications
- Signal and Clocking
- PCI Express Protocol Stack
- OSI Model and Layered Protocols
- Ethernet, Fiver Channel, TCP/IP, InfiniBand, and PCI Express Comparison
- Serial Switches
- Serial Protocol Analyzers
| | | Physical Layer | | | This chapter begins the explanation of the PCI Express Protocol Stack, starting at the bottom lf the stack with the physical layer. Bits, bytes, symbols, clocking, wire bit rate and effective bit rate, and basic electrical/mechanical requirements are presented. | | - Physical Layer
- Physical Layer Function and Services
- Logical Sub-Block
- Symbol Encoding
- Symbols, Symbol Types, and Special Character Sets
- 8B/10B Decode Rules
- Framing and Application of Symbols to Lanes
- Link Initialization, Training, TS1 and TS2 Ordered Sets
- Electrical Sub-Block
- Symbol-to-Bit and Bit-to-Symbol Conversion
- Transmit Line Requirements and Testing
- Clock Dependencies
- Recovery and Running Disparity
- Beacon and Wake# support
- Physical/Mechanical
- Connectors/Card Form Factors
- Card Detection and Hot-Plug Design Requirements
- Hot-Swap Requirements (optional feature)
- Power Management
- Native PCI Express Power Management
- Active State PM
- Add-In and System Board Requirements
- Materials, Trace Length and Routing, Signal Budgets
- Polarity Reversal, Lane Reversal
| | | Data Link Layer | | | This chapter discusses the middle layer of the PCI Express protocol stack and the two basic types of packets created and consumed at the data link layer. Data integrity, implemented in hardware, is built into this layer of the stack and described in detail. | | - Data Link Layer
- Data Link Layer Function and Services
- Data Link Control and Management State Machine
- Link Layer States
- Link Layer Rules
- Packet Format and Construction
- Link Layer Flow Control
- Initialization and Flow Control Credits
- Data Integrity
- Overview
- LCRC, Sequence Number, and Retry Management (Transmitter)
- LCRC and Sequence Number (Receiver)
- Re-Play Timer
- Recommended Priority of Scheduled Transmissions
- Physical Layer Dependencies
| | | Transaction Layer | | | All commands in PCI Express originate from the transaction layer. This chapter explains the command types, packet and field formats, and transaction usage. This chapter introduces how PCI Express defines and uses virtual channels. | | - PCI Express Transaction Layer Function and Services
- PCI Express Commands
- Transaction Layer Packet Types
- Packet Definition and Formats
- Transactions Usage and Examples
- Virtual Channels
- Virtual Channel Identification
- TC to VC Mapping and VC Rules
- Data Integrity
- ECRC Rules
- Error Forwarding
- Completion Timeout
- Link State Dependencies
| | | PCI Express Configuration Requirements | | | This chapter discusses PCI Express configuration requirements and PCI/PCI-X backwards compatibility requirements. Included are the 1.1 base specification and the ‘Trusted Configuration Environment’ requirements introduced in 2.0. | | - Configuration Mechanisms
- Legacy
- Conventional PCI Configuration Space
- Single and Multi Function Devices
- Enhanced Configuration Space
- Trusted Configuration
- Trusted devices, Trusted Platforms, Trusted Configuration Access Methods
- Root Complex Register Block and Switches
- PCI Compatible Configuration Registers
- Type 0 Headers and Type 0 Configuration Transactions
- Type 1 Headers and Type 1 Configuration Transactions
- PCIe Enumeration
- Discovery
- Addressing
- PCI-to-PCI Bridge
- Bus configuration and bus numbering
- Ordering and posting rules
- Configuration Mechanisms
- Legacy
- Enhanced Configuration Mechanism
- Root Complex Register Block
- Configuration Transaction Rules
- Device Number, Addressing, Routing
- PCI Express Extended Register Set
- Register Set Definitions, Functions and Fields
| | | Platform and System Related Issues | | | Capabilities of systems incorporating PCI Express can vary significantly depending on the platform type (portable, desktop, server, real-time process control and data acquisition systems. This chapter discusses issues that are platform and OS specific and will influence system performance. | | - PCI Express versus BIOS versus Operating System Requirements and Option
- Interrupt and PME Support
- Error Signaling and Logging
- Hardware Platform and System OS requirements
- Virtual Channel and Isochronous Support
- Within Devices, Switches, and Root Complex
- Lock Requirements
- Reset and Hot-Plug
| | | Virtual Channels and Switching | | | This chapter is a detailed dissection of the PCI Express Virtual Channel register set. The chapter discusses congestion in a serial switched environment and how PCI Express, when used properly, provides the ability to minimize and control congestion while providing guaranteed levels of system performance. | | - Properties, Characteristics, and Usage of PCI Express Virtual Channel Capabilities Register Set
- Why Virtual Channels Methods and Rules When Using VCs
- Use of Lo Priority Extended VC Count Register
- Bridge Processing versus Port and VC Buffering and Arbitration
- Fields, functions, Ranges, and Root/switch programming
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